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FPGA Acceleration Powers CHREC’s Reconfigurable Supercomputer

Case Studies
3 min read
The Novo-G supercomputer server rack alongside a Gidel PROCStar-III FPGA accelerator card. Highlights key specs including 25.6 Gb/s intel-FPGA bandwidth, PCIe x8 interface, and 4GB onboard DDR2 memory for high-performance reconfigurable computing.

The new FPGA acceleration technology from Gidel enables ultra-low-latency, full-duplex connectivity for reconfigurable supercomputers. This capability allows HPC researchers to design flexible, power-efficient clusters using direct FPGA-to-FPGA links with no CPU overhead.

Learn more about Gidel’s FPGA Acceleration cards: Gidel FPGA Accelerators.

Read more about reconfigurable computing research at CHREC: National Science Foundation.

Gidel FPGA Acceleration for Reconfigurable HPC Systems

Data centers face exponential data growth and increasing power demands. Traditional CPU-based architectures struggle to scale without major increases in power and cooling. Gidel’s FPGA acceleration technology provides a high-performance alternative, offering massive parallelism with significantly lower power consumption.

Gidel’s direct FPGA connectivity replaces CPU involvement entirely, enabling real-time computation across FPGA clusters. This connectivity supports advanced topologies such as 3D and 12D Torus, and 6D or 24D Hypercube, making it ideal for HPC workloads that require extreme throughput.

CHREC Builds a Reconfigurable Supercomputer Using Gidel FPGA Boards

The Center for High Performance Reconfigurable Computing (CHREC), funded by the National Science Foundation, set out to create the fastest research-focused reconfigurable supercomputer in the world. Their goal was to evaluate architectures that deliver both high performance and low energy consumption.

Initially, CHREC researchers explored CPU-socket accelerators but encountered instability, high costs, and under-performing I/O bandwidth. They shifted toward PCIe FPGA boards and evaluated multiple vendors. After extensive testing, Gidel was selected for its performance, stability, and superior technical support.

Why Gidel Was Chosen for the Novo-G Supercomputer

  • Highest FPGA speed grades available at the time
  • Best-in-class FPGA-to-host and FPGA-to-FPGA throughput
  • Large on-board memory with low latency
  • Mature API and run-time environment for rapid development

The resulting system, called Novo-G, used hundreds of Gidel FPGA cards (ProcStar III/IV and ProceV D8). These cards were interconnected using Gidel’s direct FPGA links, forming a high-speed 3D torus network that enabled FPGA-to-FPGA computation without CPU involvement.

Diagram of the 2×4×4 Torus network topology used in the Novo-G supercomputer. Illustrates the direct FPGA-to-FPGA interconnect architecture that allows for scalable, high-speed communication without CPU overhead.
2×4×4 Torus configuration (expandable)

Record-Setting FPGA Acceleration Performance

The Novo-G cluster delivered performance thousands of times more power-efficient than conventional supercomputers. It won the 2012 Alexander Schwarzkopf Prize for technology innovation and demonstrated nearly double the performance of Anton and fifty times the performance of BlueGene/L on the 3D FFT kernel.

This success validated Gidel’s approach to high-throughput, low-latency FPGA acceleration for large-scale HPC infrastructure.

Long-Term Collaboration and Scalable Architecture

Gidel and the CHREC team have collaborated for more than a decade. According to the researchers, migrating between Gidel FPGA platforms was straightforward because the hardware architecture and API remained consistent across generations.

The design supports scalability. One Gidel FPGA board can manage a large multi-dimensional communication network, and additional nodes can be added seamlessly to expand the cluster.

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